The present invention relates to semiconductor power device technology and more particularly to improved trench MOS (metal oxide semiconductor) barrier Schottky rectifiers with planar surfaces and fabrication processes for forming the same.
Trench MOS barrier Schottky (TMBS) rectifiers are Schottky diodes that have been integrated with trench gate shielding structures (e.g., TMBS rectifiers or monolithically integrated trench gate FET and Schottky diode devices). An integrated TMBS, which typically includes a Schottky diode array that has been interspersed between MOS trenches, generally comprises a mesa structure formed in a semiconductor epitaxial layer of a semiconductor substrate. The mesa is defined by the region between one or more trenches, which are disposed in the epitaxial layer. In TMBS devices, charge coupling between majority charge carriers in a mesa disposed between trenches in the epitaxial/drift region and conductors on the sidewalls of the trenches changes the electric field profile under the Schottky contact which reduces reverse leakage current and improves breakdown properties.
Existing techniques used to fabricate TMBS rectifiers produce topographies between device structures. For example, in an active array the tops of the polysilicon gates, silicon mesa and field dielectric are irregular and not substantially flat. This irregular topography can include abrupt changes which can significantly affect device performance by increasing reverse leakage current. Further, topographies which are created between the polysilicon gates and the mesa regions or the field dielectric to the active array propagate to layers that are subsequently formed on top of the polysilicon gates and mesa regions or the field dielectric and active array. These topographies propagate to the top surfaces of the TMBS rectifiers which end up having similar topographies. The top surfaces of the TMBS rectifier can include layers such as nitride layers and solderable top metal (STM) layers which are prone to developing cracks when they have substantially non-planar topographies. The cracks that develop in the nitride and STM layers on the top of the TMBS rectifiers can propagate to the bottom part of the nitride and STM layers and reach the metal pad layer. These cracks can then increase the reverse leakage current in the TMBS rectifier which make the TMBS rectifier inoperable or reduce its performance.
These topographies can also reduce the effectiveness of solder connections made with the STM to the package. The topographies can reduce the integrity of the solder connection because the non-coplanar surface on the STM layer on top of the TMBS rectifier is not as conducive to soldering as a planar surface. Since these topographies reduce the integrity of the solder connection, the topographies also reduce the reliability of the TMBS rectifier because the solder connections on the STM surface having non-coplanar topography are not as reliable.
Further, variations in topographies which are created between the polysilicon gates and mesa can increase the chances of inducing plasma damage to the structure (shield dielectric). The damage is caused by plasma etching the polysilicon gates, which has a non-planar surface between the polysilicon and mesa regions. This plasma induced damage can further damage the TMBS rectifier while it is being fabricated. The non-uniform topographies can increase the chances of damage occurring during processes such as plasma etching. Non-uniform contours can cause charge build up during processes such as etching which can cause arcing and damage to the TMBS rectifier as it is being fabricated. Damages that occur during fabrication can reduce yields which can increase the cost of manufacturing TMBS rectifiers. Variations in the topography can also make it difficult to uniformly deposit onto or etch material from the surface. For example, variations in topography make it difficult to bring the entire surface of the substrate in the depth of field of photolithography systems, or selectively remove material based on position. These variations that occur during fabrication can lead to variations in the electrical performance of the TMBS rectifier.
Therefore, there is a need for cost effective fabrication processes and substrate structures that reduce variations in the topography surface between termination and active cells and assists in reducing reverse leakage current and improves solderability properties.